The present invention relates to an image recorder for recording an image captured by an imaging device such as a digital video camera or a digital still camera.
Recently, digital cameras and digital video cameras are commonly used. With respect to mobile phones, those capable of taking a digital image, such as a still image or a moving image, and recording such images are widely used. It is desirable to develop a multifunctional product that efficiently carries out image processing of digital images at a low cost.
FIG. 1 shows a conventional color imaging system used in a imaging device such as a digital camera. The conventional imaging system is broadly divided into an analog front end (AFE) 10 and a digital back end (DBE) 20.
The analog front end 10, which is an analog circuit for processing an analog signal, includes an optical system circuit 11, for driving an optical system such as a lens and a diaphragm, and an imaging system circuit 12, having a CCD and a timing generator (TG) for operating the CCD. The imaging system circuit 12 performs A/D conversion on a charge (analog signal) accumulated in the CCD in accordance with a pulse signal provided from the timing generator to generate digital image data and provides the digital image data to the digital back end 20.
The digital back end 20 includes a memory controller 21, a pre-process circuit 22, a color processing circuit 23, a resolution conversion circuit 24, a JPEG compression-decompression circuit 25, an encoder 26 serving as an image output circuit, an interface circuit (I/F) 27, and a control unit (CPU) 28. A buffer memory 31, such as an SDRAM, is connected to the memory controller 21 in the digital back end 20. The memory controller 21 controls writing of the image data to the buffer memory 31 and reading of the image data from the buffer memory 31.
The analog front end 10 directly provides the image data to the pre-process circuit 22 in the digital back end 20. The pre-process circuit 22 performs pre-processes such as auto exposure (AE), auto focus (AF), and auto white balance (AWB) on the received image data. The image data pre-processed in the pre-process circuit 22 is temporarily stored in the buffer memory 31 by the memory controller 21. The pre-process circuit 22 extracts image quality control information regarding brightness and hue from the image data before being performed by the pre-process, and provides to the CPU 28 an evaluation value X1 corresponding to the image quality control information.
The color processing circuit 23 receives the image data pre-processed in the pre-process circuit 22 from the buffer memory 31, performs interpolation on the relevant image data, and generates image data in RGB format.
As shown in FIG. 2, a color filter 14 in the CCD of the analog front end 10 is a Bayer array type filter. The color filter 14 transmits only light of specific color components (red (R), green (G), or blue (B)) defined for each pixel of the CCD. A charge corresponding to the light of the specific color component transmitted through the color filter is accumulated in each of the light-receiving element (pixel) of the CCD. That is, the image data obtained from each element of the CCD is the data corresponding to one color component. Thus, in the interpolation performed in the color processing circuit 23, with respect to the image data of each element possessing only the information for one color component of RGB, image data (RGB format or YCbCr format) having information for three color components is generated by calculating a correction value for the information of three color components from the color component information of the neighboring image. The color processing circuit 23 stores such image data in the buffer memory 31.
The resolution conversion circuit 24 receives the image data from the buffer memory 31 and performs a resolution conversion process on the image data to enlarge or reduce the image.
A VRAM 31a for storing display data for an image that is displayed on a display device, such as a television (TV) or a liquid crystal display (LCD), is arranged as one part of a storage region of the buffer memory 31. The VRAM 31a stores, for example, the display data, on which resolution conversion for image display is performed in the resolution conversion circuit 24. The display data is sequentially transferred to the encoder 26 by the memory controller 21 and converted to a video output signal. The video output signal is then provided to the TV or the LCD, and an image corresponding to the signal is displayed on the display device.
The JPEG compression-decompression circuit 25 compresses (codes) or decompresses (decodes) the data of the still image in accordance with the JPEG standard. The data compressed in compliance with the JPEG standard in the JPEG compression-decompression circuit 25 is transferred and recorded to an external device (PC or MEDIA) via the I/F 27.
A flash memory 32 storing a control program is connected to the CPU 28. The CPU 28 controls the imaging system by executing the control program. The CPU 28 is connected to the pre-process circuit 22, the color processing circuit 23, the resolution conversion circuit 24, the JPEG compression-decompression circuit 25, the encoder 26, and the I/F 27 to provide a control signal to each circuit and control the operation of the circuit.
A software library 28a for AE process and AWB process is incorporated in the CPU 28. The CPU 28 provides a control value Y1, which corresponds to the evaluation value X1 from the pre-process circuit 22, to the pre-process circuit 22 and the color processing circuit 23 using the software library 28a. Thus, in the pre-process circuit 22 and the color processing circuit 23, correction control (feedback, control) is performed in accordance with the control value Y1 to achieve detailed image processing.
In recent years, an image capturing device such as a digital camera that can take both a still image and a moving image has been put into practical use. FIG. 3 shows a conventional imaging system used in an image capturing device for taking both still images and moving images. The imaging system is different from that of FIG. 1 in that an MPEG 4 compression-decompression circuit 29 is added in the digital back end 20. The MPEG 4 compression-decompression circuit 29 receives moving image data from the buffer memory 31 and compresses/decompresses (codes/decodes) the moving image data in accordance with the MPEG 4 standard. In the MPEG 4 compression-decompression circuit 29, the moving image data is compressed to generate stream data in compliance with the MPEG 4 standard. Further, the stream data is decompressed to generate the moving image data.
The stream data generated in the MPEG 4 compression-decompression circuit 29 is temporarily stored in the buffer memory 31, and subsequently, transferred to an external device (PC or MEDIA) via the I/F 27. Further, the stream data input from the external device is transferred via the I/F 27 and temporarily stored in the buffer memory 31. Subsequently, the stream data is received by the MPEG 4 compression-decompression circuit 29 and decompressed into moving image data.
Japan Laid-Open Patent Publication No. 2000-196930 discloses a conventional recorder for recording an image taken with a digital camera.
In the prior art, there are no imaging systems having a circuit configuration in which image data is fed back to a stage preceding or following the pre-process circuit 22 in the data processing path.